The present invention starts out from a lateral semiconductor structure having a punch-through diode for forming a temperature-compensated voltage limitation. It is already known to use punch-through diodes for voltage limitation in silicon semiconductor structures. Punch-through diodes are p.sup.+ np.sup.+ or rather n.sup.+ pn.sup.+ silicon structures in which the width and doping of the middle region are chosen so that when a voltage is applied to the two outer layers, no avalanche effect or rather zener effect occurs. If the voltage is increased, the space charge region of the blocking pn junction expands until it contacts the opposite junction. This pn junction operated in the conducting state injects charge carriers into the field of the space charge region, i.e., the current increases significantly starting at this voltage. The current/voltage characteristic curve of a punch-through diode is, at least for certain current densities, practically independent of temperature. In the space charge region, there exists for sufficiently high current densities a linear relationship between the current and the voltage, which is known as the space charge resistance. This space charge resistance is proportional as an approximation to the square of the expansion of the middle region. Since the punch-through voltage increases more or less with the square of the width of the middle region, the space charge resistance increases linearly for increasing voltage. Here, the problem arises that for high limitation voltages, the space charge resistance increases undesirably significantly. The known punch-through diodes are thus suited only to relatively small current densities.